Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology
M. Vohrmann, P. Geisler, T. Jungeblut, U. Ruckert, in: 2017 European Conference on Circuit Theory and Design (ECCTD), IEEE, 2017, pp. 1–4.
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Konferenzbeitrag
| Veröffentlicht
| Englisch
Autor*in
Vohrmann, Marten;
Geisler, Philippe;
Jungeblut, Thorsten
;
Ruckert, Ulrich
;
Ruckert, UlrichErscheinungsjahr
Titel des Konferenzbandes
2017 European Conference on Circuit Theory and Design (ECCTD)
Seite
1-4
Konferenz
2017 European Conference on Circuit Theory and Design (ECCTD)
Konferenzort
Catania
Konferenzdatum
2017-09-04 – 2017-09-06
FH-PUB-ID
Zitieren
Vohrmann, Marten ; Geisler, Philippe ; Jungeblut, Thorsten ; Ruckert, Ulrich: Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. In: 2017 European Conference on Circuit Theory and Design (ECCTD) : IEEE, 2017, S. 1–4
Vohrmann M, Geisler P, Jungeblut T, Ruckert U. Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. In: 2017 European Conference on Circuit Theory and Design (ECCTD). IEEE; 2017:1-4. doi:10.1109/ECCTD.2017.8093232
Vohrmann, M., Geisler, P., Jungeblut, T., & Ruckert, U. (2017). Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology. In 2017 European Conference on Circuit Theory and Design (ECCTD) (pp. 1–4). Catania: IEEE. https://doi.org/10.1109/ECCTD.2017.8093232
@inproceedings{Vohrmann_Geisler_Jungeblut_Ruckert_2017, title={Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology}, DOI={10.1109/ECCTD.2017.8093232}, booktitle={2017 European Conference on Circuit Theory and Design (ECCTD)}, publisher={IEEE}, author={Vohrmann, Marten and Geisler, Philippe and Jungeblut, Thorsten and Ruckert, Ulrich}, year={2017}, pages={1–4} }
Vohrmann, Marten, Philippe Geisler, Thorsten Jungeblut, and Ulrich Ruckert. “Design-Space Exploration of Ultra-Low Power CMOS Logic Gates in a 28 Nm FD-SOI Technology.” In 2017 European Conference on Circuit Theory and Design (ECCTD), 1–4. IEEE, 2017. https://doi.org/10.1109/ECCTD.2017.8093232.
M. Vohrmann, P. Geisler, T. Jungeblut, and U. Ruckert, “Design-space exploration of ultra-low power CMOS logic gates in a 28 nm FD-SOI technology,” in 2017 European Conference on Circuit Theory and Design (ECCTD), Catania, 2017, pp. 1–4.
Vohrmann, Marten, et al. “Design-Space Exploration of Ultra-Low Power CMOS Logic Gates in a 28 Nm FD-SOI Technology.” 2017 European Conference on Circuit Theory and Design (ECCTD), IEEE, 2017, pp. 1–4, doi:10.1109/ECCTD.2017.8093232.
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